Optimized 4-Parallel 1024-Point MSC FFT

Abstract

This paper presents a 4-parallel 1024-point multi-path delay commutator (MSC) fast Fourier transform (FFT) architecture. The aim of this work is to provide multiple optimizations of this type of FFT at the architectural level. This results in a highly optimized FFT architecture that uses significantly fewer resources than previous ones. One advantage of the proposed approach is that it uses two identical processing modules, which simplifies the development of architecture. Between the modules, instead of permutation circuits, we use matrix transposition with memories, which results in a more compact and hardware-efficient solution. Additionally, a tailor-made design of the rotations and the application of shift-and-add techniques lead to a reduction in their number and complexity. Experimental results show that the proposed architecture requires significantly fewer hardware components than previous comparable parallel pipeline FFT architectures.