Hardware Implementation of Artificial Neural Network Training Using Particle Swarm Optimization on FPGA

Abstract

In this study, a new ANN training approximation on FPGA is presented using parallel processes according to the nature of ANN. Training is implemented on FPGA using particle swarm optimization (PSO) stochastic search algorithm which does not need any derivative information. All related parameter values and processes are defined with IEEE 754 floating point numbers format. Proposed approach has been realized on Altera EP2C35F672C6 FPGA based on a sample ANN architecture using VHDL language. Obtained results show that proposed approach has successfully achieved ANN training.